1. Field of the Disclosure
The present disclosure relates to electronic devices, more particularly, to electronic devices including semiconductor fins and processes for forming the electronic devices.
2. Description of the Related Art
An electronic device can have a semiconductor fin that can act as a part of an electronic component, such as a transistor, a resistor, a capacitor, or any combination thereof. A device design can include channel regions of both conductivity types, fin and planar component structures, fins of more than one height, or any combination thereof within the same electronic device. Carrier mobility within a channel region can be affected by adjusting materials characteristics of the semiconductor material such as dopant type, dopant concentration, crystal orientation, intrinsic stress, or any combination thereof. Formation of areas with substantially different materials characteristics at specific transistor locations on a substrate can add complexity and expense to the manufacturing process. Such transistor locations can vary widely from mask set to mask set complicating the process of purchasing preformed or predefined substrates.
One proposed approach is to use additional processing and selectively thin a semiconductor region, such that a relatively shorter semiconductor-fin can be formed in the thinner semiconductor region and a relatively taller semiconductor fin can be formed in another semiconductor region. However, this does not address the need for materials differences without the addition of considerable complexity to the manufacturing process.
A double semiconductor-on-insulator (SOI) substrate has been proposed for planar devices, the double SOI substrate including a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer overlies a base layer, and the second semiconductor layer overlies the first semiconductor layer. A first insulating layer can lie between the base layer and the first semiconductor, and a second insulating layer can lie between the first and the second semiconductor layers. The double SOI substrate can address the issues with carrier mobility in the channel region. However, the thickness of each of the first and second semiconductor layers can be the full height of the tallest structure formed from that layer. The top surface of a channel region formed from the first semiconductor layer can be separated in elevation from the top surface of a channel region formed from the second semiconductor layer by the combined thickness of the second semiconductor layer and the second insulating layer. Such a difference in elevation can be problematic for integration with lithography and planarization processes.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention. The use of the same reference symbols in different drawings indicates similar or identical items.